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USB slave fifo固件程序

USB  slave fifo固件程序...
  汇编语言        ASM     

Cypress CY7C68013 USB上位机程序参考设计

TUsb_read.rar - 用VC开发的实现CY7C68013USB读取的界面,非常简单!欢迎下载。谢谢大家的支持。...
  界面开发        C++     

fifo的IP核的调用和仿真

fifo的IP的调用在我们的项目中能够缩短设计周期,省去了编写代码的复杂过程,也省去了调试程序的复杂程度和代码的复杂程度。这个小小的简单的fifo的IP核的调用能够让大家更清晰明了的理解fifo的工作原理和IP核调用的方法。...
  Verilog      Verilog     

同步fifo的C++实现

与硬件实现作对比,可以在路由算法里实现数据的收发。简单的建模模型,确是很有帮助。 文件:fifo.H,fifo.CPP,MAIN.CPP...
  其他项目        C++     

DE2_115_TV开发板例程,含SDRAM及异步fifo应用

DE2_115_TV开发板例程,含SDRAM及异步fifo应用: 通过协调器控制2入2出共4个fifo操作SDRAM...
  Verilog      Verilog     

同步fifo的状态机实现

简单状态机描述的同步fifo,包括读写计数器,空满标志位的控制。可实现顺序读写数据,包括测试文件,仿真结果正确。 filelist:fifo.v,fifo_test.v...
  Verilog      Verilog     

I2C slave AND I2C Master

里面包含I2C slave以及I2C Master,并且包含仿真程序以及波形文件,本人看了一下,特别好理解...
  Verilog      Verilog     

aynchronous fifo 项目

先入先出 (fifo) 内存结构广泛用于缓冲处理块之间的数据传输。高性能、 高复杂度数字系统越来越多地被要求不同的模块之间传输数据,甚至不相关的时钟频率。双时钟 fifo 是一个更复杂的函数,可提供高速数据缓冲对于异步时...
  Verilog      Verilog     

fifo页面置换算法

×fifo页面置换算法 例如:进程P有5个页,进程访问页的顺序为:1,2,3,4,1,2,5,1,2,3,4,5;如果在内存中分配给该进程3个页面,则缺页情况...
  Windows开发        C++     

fx2 slave fifo FPGA source code

Hi. Here's fx2 slave fifo FPGA source code...
  图像处理        C     

8051 slave UART C 代码

接收到的数据通过 UART 通信是在 SBUF 寄存器...
  嵌入式系统        C     

异步fifo

这是一个异步的fifo模块,还有5个部分,比较器,写满读空状态标志,和一个RAM模块,是编写一些大型程序的基础模块。谢谢大家,期望大家能够用得着...
  Verilog      Verilog     

先进先出fifo协议仿真

The model contains three modules. The "gen" module generates jobs, and sends them to the "fifo" module which is a single-server queue. Jobs are stored in a queue (cQueue object) until they are served -- this queue can be found and inspected in the graphical environment among the class members of...
  算法        C++     

UART Verilog sorce code and Simulation code and fifo code

 It is programed by verilog language and main code is UART, The main source code are uart_receiver.v /uart_transmitter.v/lpm_mux0.v/myfifo.v....... some wave file can help you understand more simulation information....
  Verilog      Verilog     

跨时钟域的异步fifo设计

跨时钟域的异步fifo设计设计一个fifo是ASIC设计者遇到的最普遍的问题之一。本文着重介绍怎 样设计fifo——这是一个看似简单却很复杂的任务。    一开始,要注意,fifo通常用于时钟域的过渡,是双时钟设计。换句话说...
  Verilog      Verilog     

async fifo

`timescale 1ns/1ps   13   14 module afifo   15   #(parameter    DATA_WIDTH    = 8,   16                  ADDRESS_WIDTH = 4,   17  &nbs...
  Verilog      Verilog     

verification environment to verify synchronous fifo

-> verification environment of synchronous fifo. -> universal verification methodology used. -> Assertion based verification. -> perl script included to run environment....
  Verilog      Verilog     

自定义IP-fifo

该程序模块详细介绍了自定义缓存模块fifo的设计过程,正在学习自定义FIFO模块并挂载在avalon总线上用作缓存的读者可参考该程序。...
  嵌入式系统      Verilog     

IEC 870-5-101 master&slave Simulators

One solution contains two VC++ projects (MS Visual studio 2008): IECMaster - simulator of IEC 870-5-101 communication protocol in MASTER mode,  IECslave - the same in slave mode.  Modbus - Modbus communication protocol library sources (used low level COM port routines)...
  通信        C++     

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